PLL synthesizer design

“ Control by design ”

Telestrian offers specialist PLL design and optimization service to Clients. All types of PLLs can be designed: the most common application is for the control of signal sources.

PLL design

Synthesizers are often designed by trial and error using 'rules of thumb'. Analytical design methods are now presented in a variety of documents and web based tools. These simplify the design process by enabling accurate simulation. However, real performance is often found to be below simulated or desired results.

PLL operation

Phase locked loops operate as closed loop control systems. Typically, simulation generates a design, then measurements of spectrum peaking, phase noise profile, lock time and perceived stability are used to measure performance.

An incorrect phase margin or a noisy element within the loop can remain undetected, and in turn may cause problems with adjacent channel selectivity, adjacent channel power, or EVM.

Measured open loop

The phase margin and loop bandwidth relate to the open loop system which is used for simulation and is not normally measured. It is possible to simulate the open loop system in Microwave Office™ and then measure it, by the insertion of signals into the loop, which shows the actual open loop gain and phase responses with their corresponding phase margin and gain margin. This is extremely useful for stability analysis.

This method also makes the open loop response measurable for other types of control loop systems, such as levelling, power control, linear regulators or switched mode regulators.

This enables a far greater insight into system performance. The open loop response is obtained by extracting the measurement from the system while the loop is in closed loop conditions by using the Agilent 89441A VSA.

Phase noise

Phase noise is simulated using Microwave Office™. This enables optimization and EVM analysis to be simulated alongside phase noise profiles in real time.

The models for both active and passive loops allow noise analysis of each of the individual noise sources in the system, allowing rapid simulation of topology changes. Measurement of individual system blocks is often made, to obtain the closest possible simulation of the real system.

Phase noise is measured by the Agilent E5501B phase noise test system. The dynamic range available by using this system is greater than using other measurement techniques, which means problems with the PLL will be seen, that may have been missed using conventional spectrum analysers.

Frequency offsets of up to 100 MHz can be measured of RF sources up to 6 GHz using the HP8665B signal generator.

Lock time

The system's time to achieve phase or frequency lock is measured by a FSIQ or Agilent 89441A VSA. This parameter is largely dependent upon the loop bandwidth; however it is also affected by the phase margin.

Lock times can also be degraded by a number of factors. Normally these issues are related to the transient performance or leakage of components associated with the loop.